1. Technical Field
This invention relates generally to programmable semiconductor memories, and more particularly, to the configuration of a memory device incorporating flash memory cells.
2. Cross-Reference to Related Case
This case is related to FLASH MEMORY ARRAY ARCHITECTURE AND METHOD OF PROGRAMMING, ERASING, AND READING THEREOF, invented by Sameer Haddad, filed Dec. 11, 2001, Ser. No. 10/013,993.
3. Background Art
A type of programmable memory cell is commonly referred to as a flash memory cell. Such flash memory cell may include a source and a drain formed in a silicon substrate, or in a well that is formed in the silicon substrate. The flash memory cell includes a stacked gate structure formed on the silicon substrate. The region of the silicon substrate beneath the stacked gate structure is known as the channel region of the flash memory cell.
The stacked gate structure of the flash memory cell includes a pair of polysilicon structures separated by oxide layers. One of the polysilicon structures functions as a floating gate and the other polysilicon structure functions as a control gate for the flash memory cell. The oxide layer that separates the floating gate from the silicon substrate is commonly referred to as a tunnel oxide layer. A memory cell of this type is shown and described in U.S. Pat. No. 4,698,787, xe2x80x9cSingle Transistor Electrically Programmable Memory Device and Methodxe2x80x9d, issued to Mukherjee et al. on Oct. 6, 1987.
Programming operations on a flash memory cell involve the application of a relatively large constant voltage to the drain of the flash memory cell while an even larger voltage is applied to the control gate. During such a programming operation, the source of the flash memory cell is maintained at a ground level or a zero voltage level in relation to the voltages applied to the control gate and drain. The high constant voltage applied to the control gate raises the voltage potential of the floating gate to a high level at the start of the programming operation. Such a high voltage potential on the floating gate attracts the electrons floating through the channel region. Under these conditions, electrons in the channel region having sufficiently high kinetic energy migrate through the tunnel oxide layer and onto the floating gate. This phenomenon is commonly referred to as hot carrier programming or hot carrier injection. A successful programming operation involves the injection of sufficient numbers of electrons onto the floating gate to achieve a desired threshold voltage for the flash memory cell. The threshold voltage is the voltage that must be applied to the control gate of the flash memory cell to cause conduction through the channel region during the read operation on the flash memory cell.
In a typical memory array which includes a large number of cells, a cell can be programmed by applying programming voltages of approximately 9-10 volts to the control gate, approximately 5 volts to the drain, and grounding the source. These voltages cause hot electrons to be injected from a drain depletion region into the floating gate. Upon removal of the programming voltages, the injected electrons are trapped in the floating gate and create a negative charge therein that increases the threshold of the cell to a value in excess of approximately 4 volts.
A cell can be read by applying a voltage of approximately 5 volts to the control gate, applying approximately 1 volt to the bit line to which the drain is connected, grounding the source, and sensing the bit line current. If the cell is programmed and the threshold voltage is relatively high (5 volts), the bit line current will be zero or relatively low. If the cell is not programmed or is erased, the threshold voltage will be relatively low (2 volts), the control gate voltage will enhance the channel, and the bit line current will be relatively high.
A cell can be erased in several ways. In one approach, applying a relatively high voltage, typically 12 volts, to the source, grounding the control gate and allowing the drain to float erases a cell. This causes the electrons that were injected into the floating gate during programming to undergo Fowler-Nordheim tunneling from the floating gate through the thin tunnel oxide layer to the source. Applying a negative voltage on the order of xe2x88x9210 volts to the control gate, applying 5 volts to the source and allowing the drain to float can also erase the cell. Another method of erasing a cell is by applying 5 volts to the P well and xe2x88x9210 volts to the control gate while allowing the source and drain to float.
In such a typical prior art cell, during the programming of a cell, a relatively high voltage of 9-10 volts is applied to the control gate. In a modern memory array wherein the supply voltage is for example 5 volts, providing this relatively high voltage to the control gate for proper programming of the cell has proven problematical. This is because the ability to provide voltages within the circuit which are higher than the supply voltage is greatly limited. However, with a typical supply voltage of for example 5 volts, and with 5 volts applied to the control gate of the transistor to be programmed, the electric field formed by the applied voltages to induce hot electrons to be injected from the drain depletion region into the floating gate is insufficient to cause the cell to be programmed properly and in a rapid manner.
Therefore, what is needed is a method for programming cells of a memory array which provides an effective and rapid programming thereof, meanwhile with the supply voltage to the memory array being low.
In the present method of programming a memory cell of a flash EEPROM memory cell array, the array is defined in a semiconductor substrate. The cell includes in the substrate an N type source, a P type channel, and an N type drain. A floating gate is positioned over the channel, and a control gate is positioned over the floating gate. In the present method, a positive voltage is applied to the drain of the cell to be programmed, a voltage lower than the voltage applied to the drain is applied to the source of the selected cell, a negative voltage is applied to the substrate, and a positive voltage is applied to the control gate of the selected cell sufficient to induce hot electron injection from the drain to the floating gate of the selected cell.